Description
Hardware Description Languages (HDLs) such as SystemVerilog allow engineers to rapidly design and prototype electronic circuits. While originally intended only for simulation and verification of designs, modern synthesis tools can synthesize HDL to Field Programmable Gate Array (FPGA) configurations or even standard-cell Application-Specific Integrated Circuits (ASICs). For both FPGAs and ASICs, the options for debugging a design in hardware are fairly limited. At the same time, especially for ASICs, changes after tape-out (manufacturing of the first ASIC) are prohibitively expensive. Thus, functional verification (i.e., testing of the design before synthesis) is crucial for avoiding bugs to propagate into the actual hardware.
However, existing methodologies commonly rely on constrained-random generation of test cases only. Thereby, computational effort of verification is high, and there is no guarantee that all valid test cases will be generated during the verification run time. Anecdotal evidence also suggests that
constrained-random solvers tend to only cover a subset of the valid input space under certain conditions.
For the purpose of functional verification, verification languages such as SystemVerilog include language constructs for user-defined input constraints and collecting functional coverage. Thus, this project aims at exploiting these features to enable a fuzzing approach for the generation of test cases, aiming at faster completion of functional verification. To this end, the existing input constraints can serve as corpus for the fuzzer, while functional coverage can serve as feedback.