Context-Switching Instruction for RISC-V
Description
Context switching in RISC-V is an expensive operation: the dispatcher needs to copy all registers of the current thread into a thread control block, flush the caches, configure the MMU and restore the registers of the thread to be run. This is exacerbated by RISC-V’s large register set (32 registers plus floating point registers). ARM CPUs have instructions that can transfer multiple registers at once (e.g., STM), which is especially useful for increasing performance of context switches. On systems with AXI buses in particular, all registers can be read and written in a single memory transaction, saving the cycles needed for starting and terminating the transactions for individual transfers. This project aims at adding an equivalent instruction of STM to a RISC-V CPU and evaluating its effectiveness in reducing context switch overhead empirically.
Outline
- design load multiple / store multiple instructions for RISC-V
- implement these instructions in a RISC-V CPU, e.g., cva6
- possibly, the instructions can be implemented in a standard RISC-V coprocessor
- conduct micro-benchmark of the instructions’ effectiveness in an OS like Linux or zephyr
Intended Scope
Master thesis
References / Extra Material
- ARM STM instruction: https://developer.arm.com/documentation/ddi0406/b/Application-Level-Architecture/Instruction-Details/Alphabetical-list-of-instructions/STM---STMIA---STMEA
- CVA6 RISC-V CPU: https://github.com/openhwgroup/cva6
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